A phase lock loop (PLL) circuit is configured to generate an output clock signal that is frequency and phase locked with an input reference clock signal. A PLL circuit typically includes a phase detector for generating a signal indicative of a phase difference between a feedback clock signal and the reference clock signal, a phase/frequency error signal generating device, a voltage controlled oscillator (VCO) for generating the output clock signal based on the phase/frequency error signal, and a frequency divider for generating the feedback clock signal by frequency dividing the output clock signal. Through negative feedback operation, the phase/frequency error signal forces the VCO to generate the output or VCO clock signal to be phase and frequency locked with the reference clock signal.
The PLL circuit may further include a calibration circuit for setting an initial frequency for the output clock signal generated by the VCO prior to the phase/frequency control of the output clock signal as discussed above. In the past, the calibration circuit included substantial electronics for setting the initial frequency of the VCO clock signal. Such additional calibration electronics typically consumes substantial power, requires substantial integrated circuit (IC) footprint to implement, and requires a relatively long calibration procedure to set the initial frequency of the VCO clock signal.